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1/20 may 2002 M68AF031AL 256 kbit (32k x 8) 5.0v asynchronous sram features summary n supply voltage: 4.5 to 5.5v n 32k x 8 bits sram with output enable n equal cycle and access time: 70ns n low standby current n low v cc data retention: 2v n tri-state common i/o n automatic power down figure 1. packages 28 1 pdip28 (b) so28 (ms) tsop28 (n) 8 x 13.4mm tsop28 (ns) 8 x 13.4 mm (reverse)
M68AF031AL 2/20 table of contents summary description. . . . . . . . . . . . . . . . . . ....... ..................................3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . ..................................3 figure 3. so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... ............4 figure 4. dip connections . . . . . . . . . . . . . . . . . . . . . . ............................ ......4 figure 5. tsop connections (normal) . . . . . . . ........................................4 figure 6. tsop connections (reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ ......5 table 2. absolute maximum ratings. . . . . . . . . . . . . . . ..................................5 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. operating and ac measurement conditions. . ............................ ......6 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . ........................6 figure 9. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................7 table 5. dc characteristics ........................................................7 operation ......................................................................8 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 10. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 11. chip enable or output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . 9 figure 12. chip enable controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 14. chip enable controlled, write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. low v cc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . .......................14 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 so28 - 28 lead plastic small outline, 300 mils body width, package outline . . . . . . . . . . . . . . . . 15 so28 - 28 lead plastic small outline, 300 mils body width, package mechanical data . . . . . . . . . 15 pdip28 - 28 pin plastic dip, 600 mils width, package outline . . . . . . . . . . . . . ...............16 pdip28 - 28 pin plastic dip, n600 mils width, package mechanical data . . . . . . . . . . . . . . . . . . . 16 tsop28 - 28 lead normal and reverse pinout plastic small outline, package outline . . . . . . . . 17 tsop28 - 28 lead normal and reverse pinout plastic small outline, package mechanical data. 17 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18 table 13. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. ..............................................................19 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20 M68AF031AL summary description the M68AF031AL is a 256 kbit (262,144 bit) cmos sram, organized as 32,768 bytes. the de- vice features fully static operation requiring no ex- ternal clocks or timing strobes, with equal address access and cycle times. it requires a single 4.5 to 5.5v supply. this device has an automatic power- down feature, reducing the power consumption by over 99% when deselected. the M68AF031AL is available in so28 (28-lead small outline), pdip28 (28-pin plastic dual-in- line) and tsop28 (28-lead thin small outline, standard and reverse pinout) packages. figure 2. logic diagram table 1. signal names ai05920 16 a0-a14 w dq0-dq7 v cc M68AF031AL g 8 e v ss a0-a14 address inputs dq0-dq7 data input/output e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally
M68AF031AL 4/20 figure 3. so connections figure 4. dip connections figure 5. tsop connections (normal) figure 6. tsop connections (reverse) v ss a12 dq0 dq1 dq2 a13 a14 a0 dq4 e dq7 g dq6 dq5 dq3 a3 w a6 a11 a5 v cc a8 ai05921 M68AF031AL 8 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 a9 a10 22 21 20 19 18 17 a1 a2 1 a7 a4 ai05922 M68AF031AL 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 a0 dq4 e dq7 g dq6 dq5 dq3 a3 w v cc a1 a2 a4 v ss a12 dq0 dq1 dq2 a13 a14 a6 a11 a5 a8 a9 a10 a7 e a14 a10 g a12 a3 a13 a2 a1 dq6 a4 a11 a0 dq7 dq4 dq0 dq1 dq3 v ss dq5 a6 a5 a7 a9 w v cc a8 ai07200 M68AF031AL (normal) 1 7 28 22 21 15 14 8 dq2 e dq7 a1 ga0 a8 a13 a9 a10 dq0 a7 a11 a12 a14 dq2 dq6 dq5 dq3 v ss dq1 a6 a5 a4 a2 w v cc a3 ai07201 M68AF031AL (reverse) 1 7 28 22 21 15 14 8 dq4
5/20 M68AF031AL figure 7. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for periods greater than 1 sec periods may affect device reliability. refer also to the stmicro- electronics sure program and other relevant quality documents. table 2. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. up to a maximum operating v cc of 6.0v only. ai05919 row decoder a7 a14 dq0 dq7 column decoder i/o circuits a0 a6 w g memory array e symbol parameter value unit i o (1) output current 20 ma p d power dissipation 1 w t a ambient operating temperature 55 to 125 c t stg storage temperature 65 to 150 c v cc supply voltage 0.5 to 6.5 v v io (2) input or output voltage 0.5 to v cc +0.5 v
M68AF031AL 6/20 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit parameter M68AF031AL v cc supply voltage 4.5 to 5.5v ambient operating temperature range 1 0 to 70 c range 6 40 to 85 c load capacitance (c l ) 100pf output circuit protection resistance (r 1 ) 3.0k w load resistance (r 2 ) 3.1k w input and output timing ref. voltages v cc /2 input rise and fall times 1ns/v input pulse voltages 0tov cc output transition timing ref. voltages v rl = 0.3v cc ;v rh = 0.7v cc ai05831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai05932 v cc out c l includes probe capacitance device under test c l r 1 r 2
7/20 M68AF031AL table 4. capacitance note: 1. sampled only, not 100% tested. 2. at t a =25 c, f = 1 mhz, v cc = 5.0v. table 5. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e = v il ,v in =v il or v ih . 3. e 0.2v, v in 0.2v or v in v cc 0.2v. 4. output disabled. symbol parameter (1,2) test conditio n min max unit c in input capacitance on all pins (except dq) v in =0v 6pf c out output capacitance v out =0v 8 pf symbol parameter test condi tion min typ max unit i cc1 (1,2) operating supply current v cc = 5.5v, f = 1/t avav , i out =0ma 50 ma i cc2 (3) operating supply current v cc = 5.5v, f = 1mhz, i out =0ma 5ma i sb standby supply current cmos v cc =5.5v,f=0, e v cc 0.2v range 1 0.1 5 m a range 6 0.1 10 m a i li input leakage current 0v v in v cc 1 1 m a i lo (4) output leakage current 0v v out v cc 1 1 m a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage 0.3 0.8 v v oh output high voltage i oh = 1.0ma 2.4 v v ol output low voltage i ol = 2.1ma 0.4 v
M68AF031AL 8/20 operation the M68AF031AL has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e = high). an output enable (g) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common i/o data bus. operational modes are determined by device con- trol inputs w and e, as summarized in the operat- ing modes table (see table 6). table 6. operating modes note: 1. x = v ih or v il . read mode the M68AF031AL is in the read mode whenever write enable (w) is high with output enable (g) low, and chip enable (e) is asserted. this pro- vides access to data of the 262,144 locations in the static memory array, specified by the 15 ad- dress inputs. valid data will be available at the eight output pins within t avqv after the last stable address, providing g is low and e is low. if chip enable or output enable access times are not met, data access will be measured from the limit- ing parameter (t elqv or t glqv ) rather than the ad- dress. data out may be indeterminate at t elqx and t glqx but data lines will always be valid at t avqv . figure 10. address controlled, read mode ac waveforms note: e = low, g = low, w = high. operation e w g dq0-dq7 power deselected v ih x x hi-z standby (i sb ) read v il v ih v il data output active (i cc ) write v il v il x data input active (i cc ) output disabled v il v ih v ih hi-z active (i cc ) ai05939 tavav tavqv taxqx a0-a14 dq0-dq7 valid data valid
9/20 M68AF031AL figure 11. chip enable or output enable controlled, read mode ac waveforms. note: writ e enable (w) = high. figure 12. chip enable controlled, standby mode ac waveforms ai05940 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a14 e g dq0-dq7 valid ai05956 tpd i cc tpu i sb 50% e
M68AF031AL 10/20 table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. tested initially and after any design or process changes that may affect these parameters. symbol parameter M68AF031AL unit 70 t avav read cycle time min 70 ns t avqv address valid to output valid max 70 ns t axqx (1) data hold from address change min 10 ns t ehqz (2,3) chip enable high to output hi-z max 25 ns t elqv chip enable low to output valid max 70 ns t elqx (1) chip enable low to output transition min 10 ns t ghqz (2,3) output enable high to output hi-z max 25 ns t glqv output enable low to output valid max 35 ns t glqx (1) output enable low to output transition min 5 ns t pd (4) chip enable high to power down max 0 ns t pu (4) chip enable low to power up min 70 ns
11/20 M68AF031AL write mode the M68AF031AL is in the write mode whenever the w and e are low. either the chip enable input (e) or the write enable input (w) must be de- asserted during address transitions for subsequent write cycles. when e (w) is low, write cycle begins on the w (e)'s falling edge. therefore, address setup time is referenced to write enable or chip enable as t avwl and t avel respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e or w. if the output is enabled (e = low, g = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e, whichever occurs first, and remain valid for t whdx and t ehdx respectively. figure 13. write enable controlled, write ac waveforms note: 1. during this period dq0-dq7 are in output state and input signals should not be applioed. ai05941 tavav twhax tdvwh data input a0-a14 e w dq0-dq7 valid tavwh twlwh tavwl twlqz twhdx twhqx telwh data (1) data (1)
M68AF031AL 12/20 figure 14. chip enable controlled, write ac waveforms ai05942 tavav tehax tdveh a0-a14 e w dq0-dq7 valid taveh tavel teleh tehdx data input twleh
13/20 M68AF031AL table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. symbol parameter M68AF031AL unit 70 t avav write cycle time min 70 ns t aveh address valid to chip enable high min 60 ns t avel address valid to chip enable low min 0 ns t avwh address valid to write enable high min 60 ns t avwl address valid to write enable low min 0 ns t dveh input valid to chip enable high min 30 ns t dvwh input valid to write enable high min 30 ns t ehax chip enable high to address transition min 0 ns t ehdx chip enable high to input transition min 0 ns t eleh chip enable low to chip enable high min 60 ns t elwh chip enable low to write enable high min 60 ns t whax write enable high to address transition min 0 ns t whdx write enable high to input transition min 0 ns t whqx (1) write enable high to output transition min 5 ns t wleh write enable low to chip enable high min 60 ns t wlqz (1,2) write enable low to output hi-z max 25 ns t wlwh write enable low to write enable high min 60 ns
M68AF031AL 14/20 figure 15. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih v cc 0.2v or v il 0.2v. 2. tested initially and after any design or process changes that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 2.0v, e v cc 0.2v, f = 0 (3) 6 m a t cdr (1,2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e v cc 0.2v, f = 0 2.0 v ai05925 data retention mode tr 5.5v tcdr v cc 4.5v v dr > 2.0v e e v dr 0.2v
15/20 M68AF031AL package mechanical figure 16. so28 - 28 lead plastic small outline, 300 mils body width, package outline note: drawing is not to scale. table 10. so28 - 28 lead plastic small outline, 300 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.38 2.79 0.094 0.110 a1 0.05 0.35 0.002 0.014 a2 2.28 2.43 0.090 0.096 b 0.35 0.50 0.014 0.020 c 0.20 0.30 0.008 0.012 d 18.03 18.41 0.710 0.725 ddd 0.10 0.004 e 7.39 7.62 0.291 0.300 e 1.27 0.050 h 11.68 12.19 0.460 0.480 l 0.79 1.27 0.031 0.050 a 0 8 0 8 n28 28 e 14 e d c h 15 28 1 b so-e a1 l a1 a hx45 a ddd
M68AF031AL 16/20 figure 17. pdip28 - 28 pin plastic dip, 600 mils width, package outline note: drawing is not to scale. table 11. pdip28 - 28 pin plastic dip, n600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 36.83 37.34 1.450 1.470 d2 33.02 1.300 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 14.99 0.590 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.08 0.070 0.082 a 0 10 0 10 n28 28 pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
17/20 M68AF031AL figure 18. tsop28 - 28 lead normal and reverse pinout plastic small outline, package outline note: drawing is not to scale. table 12. tsop28 - 28 lead normal and reverse pinout plastic small outline, package mechanical data symbol millimeters inches typ min max typ min max a 1.250 0.0492 a1 0.200 0.0079 a2 0.950 1.150 0.0374 0.0453 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 13.200 13.600 0.5197 0.5354 d1 11.700 11.900 0.4606 0.4685 e 7.900 8.100 0.3110 0.3189 e 0.550 0.0217 l 0.500 0.700 0.0197 0.0276 a 0 5 0 5 n28 28 tsop-c d1 e 78 cp b e a2 a 22 d die c l a1 a 21 28 1
M68AF031AL 18/20 part numbering table 13. ordering information scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m68af031 a l 70 ms 6 t device type m68 mode a = asynchronous operating voltage f = 4.5 to 5.5v array organization 031 = 256 kbit (32k x8) optio n 1 a = 1 chip enable optio n 2 l = low leakage speed class 70 = 70 ns package ms = so28 b = pdip28 n = tsop28 8x13.4mm ns = tsop28 8x13.4mm (reverse pinout) operative temperature 1=0to70 c 6=40to85 c shipping t = tape & reel packing
19/20 M68AF031AL revision history table 14. document revision history date version revision details january 2002 -01 first issue 07-feb-2002 -02 i sb clarified 08-feb-2002 -03 tsop28 package removed ac measurement load circuit changed (figure 9) operating and ac measurement conditions clarified (table 3) 06-mar-2002 -04 document status changed to data sheet 19-apr-2002 -05 absolute maximum current value added (table 2) operating and ac measurement conditions clarified (table 3) 26-apr-2002 -06 absolute maximum ratings table clarified (table 2) operating and ac measurement conditions table clarified (table 3) dc characteristics table clarified (table 5) write mode ac characteristics table clarified (table 8) low v cc data retention ac waveforms clarified (figure 15) low v cc data retention characteristics table clarified (table 9) 20-may-2002 -07 dc characteristics table clarified (table 5) low v cc data retention characteristics table clarified (table 9) 29-may-2002 -08 tsop28 8x13.4mm standard and reverse pinout added (figure 1, 5, 6, table 12)
M68AF031AL 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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